By Elie Maricau
This ebook makes a speciality of modeling, simulation and research of analog circuit getting older. First, all very important nanometer CMOS actual results leading to circuit unreliability are reviewed. Then, transistor getting older compact types for circuit simulation are mentioned and several other equipment for effective circuit reliability simulation are defined and in comparison. eventually, the influence of transistor getting older on analog circuits is studied. Aging-resilient and aging-immune circuits are pointed out and the influence of know-how scaling is mentioned.
The versions and simulation thoughts defined within the publication are meant as an reduction for equipment engineers, circuit designers and the EDA group to appreciate and to mitigate the effect of getting older results on nanometer CMOS ICs.
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Additional resources for Analog IC Reliability in Nanometer CMOS
Time-Dependent Dielectric Breakdown The correct operation of a MOS transistor relies on the insulating properties of the dielectric layer below the gate electrode of the transistor (Stathis 2001). Each dielectric material has a maximum electric field it can sustain. 4 Temporal Unreliability 27 Fig. 8 Multiple breakdown spots at the drain junction of an nMOS transistor. Note the thermal damage to the silicon. Source Yazdani (2011) field is applied, this leads to hard breakdown (HBD). 3 At lower electric fields, the insulator can wearout after some time and finally break down completely.
For smaller transistor dimensions, on the other hand, CHE dominates the hot carrier degradation effect (Takeda et al. 1983). 002 0 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 Stress time [s] Fig. 7 Hot carrier injection (HCI) is typically modeled with a power law time dependence. 0 V, is depicted (Maricau et al. 2008) HCI is typically modeled with a power law dependence on the stress time (see Fig. 7) (Hu et al. 1985; Kufluoglu and Ashraful Alam 2004; Maricau et al. 5 (Hu et al. 1985). The trapping generation of the carriers increases exponentially with increasing oxide electric field (E ox ).
The trapping generation of the carriers increases exponentially with increasing oxide electric field (E ox ). Besides the oxide electric field and the maximum lateral electric field (E lat ), HCI dependence on temperature (T ) and transistor length (L) has also been reported (Hu et al. 1985; Wang et al. 2007; Maricau et al. 4) with αHCI,1 and αHCI,2 technology-dependent parameters. 4), HCI also introduces an extra source of variability, due to the randomly generated traps in the gate dielectric or at the substrate/dielectric interface.
Analog IC Reliability in Nanometer CMOS by Elie Maricau